This invention relates generally to RF power transistor arrays, and more particularly the invention relates to thermally balancing large-area, multi-cell transistor arrays.
Conventional power transistors comprise a cellular semiconductor die whose multiple device cells are interconnected in parallel. A common problem in such structures is thermal imbalances that result when individual devices in the multi-cell array operate unevenly. In the extreme, this condition results in thermal runaway, where collector current increases until device failure occurs.
A more common thermal instability is due to an internal thermal imbalance which causes the minority carrier collector current in a cell to crowd into one small portion of the active region and results in hot spots. If the temperature differential of the hot spot is great enough at sufficient high dissipation, a discontinuous change in the electrical characteristics of the transistor can occur, due to localized melting of the semiconductor.
These effects occur because the DC collector current of a transistor increases as the junction temperature increases. There are several sources of this positive temperature coefficient of collector current:
(1) If the base current is constrained by the circuit to be constant, the collector current increases with temperature because the DC common-emitter current gain increases with temperature. PA1 (2) If the emitter-base voltage is constrained by the circuit to be constant, the emitter current, and thus the collector current, increases exponentially with temperature at a rate of about 8% per degree C.
Typical methods for connecting silicon RF power devices thermal imbalance involve the use of resistance losses (or feedback) to distribute the collector or emitter current more equally within the multi-cell structure. Two kinds of "ballast" resistor techniques are consistently used: emitter ballast or collector ballast. The emitter ballast technique consists of adding a small amount of lumped resistance in series with emitter sites before they are bussed together by interconnecting metallization and bondwires. Several Types of emitter ballast methods are used. The most common method involves an emitter resistor connected in series with each emitter finger. This resistor can be either a thin-film resistor or a diffused resistor.
Thin-film resistors are formed by etching gold (or other conductor metal, for example, aluminum) off of the emitter metal stripe, leaving a refractory barrier metal, which has high resistivity. Diffused resistors, as the name implies, are formed by a diffusion into the silicon crystal, which is contacted by the emitter metallization. The emitter ballast is simply an emitter feedback resistor deposited directly on the transistor chip that forces better current sharing. It also results in lower gain and somewhat higher saturation voltage.
The collector ballast technique is carried out by making the collector epitaxial region thicker than necessary in order to support the designed collector-base depletion layer. In effect, this results in a resistor in series with the collector regions under each active cell before they are electrically connected by the low-resistivity silicon substrate. The series resistance better distributes current under breakdown conditions. It also limits the current level. Collector ballast, therefore, makes the transistors more rugged under load mismatch, over-voltage, and over-drive conditions. However, while performance is improved, a lower saturated power and somewhat lower efficiency results.
Thus, there exists a need for providing a method of device ballasting that overcomes the problems and limitations attendant with prior-art techniques.